Integrated circuit memory devices such as dynamic random access memories (DRAM) can be more highly integrated by reducing the size of each memory cell thereby increasing a memory capacity thereof. In particular, dynamic random access memories have been developed with memory capacities of 16M, 64M, and even 256M. Accordingly, there continues to exist a need to provide memory cells of ever decreasing size.
A DRAM generally includes a MOS (metal oxide semiconductor) transistor and a capacitor. The capacitor includes a lower (storage) electrode and an upper (plate) electrode separated by a thin dielectric layer therebetween. The capacitance of this capacitor is proportional to the effective capacitor electrode area and inversely proportional to the distance between the two electrodes which is determined by the thickness of the dielectric layer. As it may be desirable to maintain a predetermined capacitance despite reductions in the memory cell area, it may be desirable to increase the effective capacitor electrode area per unit area of substrate, to provide a dielectric material having a relatively high permittivity, or to reduce the thickness of the dielectric layer.
Several techniques have thus been developed to provide memory cell capacitors having a predetermined capacitance on reduced areas of the substrate. In particular, capacitor electrodes having three-dimensional structures can be provided. For example, stack structures, trench structures, cylindrical structures, and capacitor over bit-line (COB) structures can be provided. These structures may be difficult to implement in highly integrated circuit memory devices, however, because of the increased expense and complexity required during manufacture. These structures may also result in design rule limitations. Furthermore, it may be difficult to obtain sufficient and stable capacitances using these structures.
Capacitor electrode surface areas have also been increased by the formation of hemispherical grained silicon layers. FIG. 1 is a flow chart illustrating steps of a method of forming a capacitor including the formation of a hemispherical grained silicon layer. FIG. 2 is a flow chart illustrating steps of a method of forming a hemispherical grained silicon layer on the lower electrode of the semiconductor capacitor.
Referring to FIG. 1, a lower electrode pattern is formed 101 wherein the lower capacitor electrode of the memory cell capacitor is electrically coupled with a source of a MOS transistor through contact holes in an insulating layer. The lower capacitor electrode can be used to store a bit of information wherein the access transistor allows data to be written to or read from the capacitor. The lower capacitor electrode can be an amorphous silicon layer formed by low pressure chemical vapor deposition wherein the amorphous silicon layer can be phosphorous doped or undoped. In addition, the insulating layer between the lower capacitor electrode and the substrate can be a silicon oxide layer. Moreover, the amorphous silicon layer can be patterned using conventional photolithography and etch steps to form the lower electrode pattern 101.
A hemispherical grained silicon layer is then formed 103 on the exposed surface of the lower capacitor electrode pattern. The formation of hemispherical grained silicon layers is discussed for example in the reference by Watanabe et al. entitled "Hemispherical Grained Silicon Formation on In-Situ Phosphorous Doped Amorphous-Si Using The Seeding Method," SSDM, 1992, pp. 422-424. The disclosure of this reference is hereby incorporated herein in its entirety by reference.
In particular, a hemispherical grained silicon layer can be formed at the transition temperature range of crystalline silicon and amorphous silicon through silicon migration so that its surface energy is stabilized. In addition, the silicon containing gas such as silane (SiH.sub.4) or disilane (Si.sub.2 H.sub.6) can provide an active reaction at the surface of the lower electrode, or silicon from within the electrode can migrate to form protrusions. In addition, seeds can be used to provide surface roughness. The capacitance of the resulting capacitor can thus be increased due to the increased surface area of the lower capacitor electrode.
Steps of a method for forming a hemispherical grained silicon layer are shown in FIG. 2. A temperature inside a high vacuum chemical vapor deposition apparatus including a resistive heating source is maintained at a constant temperature during a temperature stabilization step 111. For example, the temperature can be maintained at approximately 580.degree. C. Molecules of disilane (Si.sub.2 H.sub.6) or silane (SiH.sub.4) are then irradiated on the surface of the lower capacitor electrode to provide a seeding gas during a seeding step 113. Silane and disilane both have active surface reactions with the amorphous silicon of the electrode. A thermal treatment 115 is then carried out to form the hemispherical grained (HSG) silicon layer. The surface of the electrode is thus roughened with hemispherical grains due to the thermal migration of silicon particles. After forming the hemispherical grained silicon layer, a wet etch step 104 is performed to remove a native oxide which may form on the surface of the electrode prior to forming a nitride dielectric layer.
A nitridation step 105 is then performed on a native oxide on the surface of the lower electrode by flowing ammonia gas over the exposed portion of the electrode at a temperature of approximately 800.degree. C. A silicon nitride layer is then formed 106 on the nitrified lower electrode at a temperature in the range of 600.degree. C. to 700.degree. C.
A portion of the nitride layer is then dry-oxidized or wet-oxidized in step 107 to cure the nitride layer. Accordingly, the dielectric layer includes nitride and oxide layers. An upper capacitor electrode is then formed 108 by forming and patterning a second conductive layer.
In the method discussed above, a wet-etch is used to remove a native oxide layer prior to the formation of the nitride layer. This wet-etch step, however, may also wear down the surface of the hemispherical grained silicon layer thereby reducing a surface area thereof. The resulting capacitor may thus have a capacitance reduced by as much as ten percent. In addition, the leakage current of the resulting capacitor may be increased at the interface of the lower electrode and the hemispherical grained silicon layer because of abrasion due to the silicon etching.
Furthermore, when a hemispherical grained silicon layer is formed at the transition temperature range of crystalline silicon and amorphous silicon, the resulting hemispherical grained silicon layer may be sensitive to temperature variations. Accordingly, it may be difficult to maintain a uniform size and density of hemispherical silicon grains between wafers within a processing run and between processing runs. In other words, there may be insufficient processing margins so that undesirable variations in capacitance result.